S. Huang, S. Diao and F. Lin, “An Energy-Efficient high-speed CMOS Hybrid Comparator with reduced Delay Time in 40nm CMOS Process,” in Analog Integrated Circuits and Signal Processing, Vol. 89, no. 1, pp. 231-238, Oct. 2016.
上一篇：下一篇：
S. Huang, S. Diao and F. Lin, “An Energy-Efficient high-speed CMOS Hybrid Comparator with reduced Delay Time in 40nm CMOS Process,” in Analog Integrated Circuits and Signal Processing, Vol. 89, no. 1, pp. 231-238, Oct. 2016.
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